1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly to a driving method and device for displaying a video signal of a normal mode having an aspect ratio of 4 to 3 in a wide mode LCD device having an aspect ratio of 16 to 9.
2. Discussion of the Related Art
With development of information society, demands for various display devices increase. Accordingly, many efforts have been made to research and develop various flat display devices such as liquid crystal display (LCD), plasma display panel (PDP), electroluminescent display (ELD), and vacuum fluorescent display (VFD). Some species of the flat display devices are already applied to displays of various equipments.
Among the various flat display devices, the liquid crystal display (LCD) device has been most widely used due to the advantageous characteristics of thinness, lightness in weight, and low power consumption, whereby the LCD device substitutes for Cathode Ray Tube (CRT). In addition to the mobile type LCD devices such as a display for a notebook computer, the LCD devices have been developed for computer monitors and televisions to receive and display broadcasting signals.
In general, an LCD device includes an LCD panel for displaying a picture image, and a driving circuit for applying a driving signal to the LCD panel. The LCD panel is a display device having a liquid crystal injected between two transparent substrates (glass substrates) bonded to each other at a predetermined interval. At this time, one of the two transparent substrates includes a plurality of gate lines arranged in one direction at fixed intervals, a plurality of data lines arranged at fixed intervals for being in perpendicular to the plurality of gate lines, a plurality of pixel electrodes arranged as a matrix type in respective pixel regions defined by the plurality of gate and data lines crossing each other, and a plurality of thin film transistors being switched according to signals of the gate lines for transmitting signals of the data lines to the respective pixel electrodes. The other transparent substrate includes a color filter layer, a common electrode and a black matrix layer. Accordingly, by sequentially applying turn-on signals to the gate lines, data signals are applied to the corresponding pixel electrodes, thereby displaying the picture image.
The general LCD device having the driving circuit will be described with reference the accompanying drawings. FIG. 1 is a block diagram illustrating the driving circuit of the general LCD device. As mentioned above, the driving circuit of the LCD device includes an LCD panel 1 having pixel regions in a matrix type by arranging a plurality of gate G and data D lines crossing each other, a driving circuit part 2 for providing driving and data signals to the LCD panel 1, and a backlight 8 for providing a light source to the LCD panel 1.
The driving circuit part 2 includes a data driver 1b, a gate driver 1a, a timing controller 3, a power supply part 4, a gamma reference voltage part 5, an AC/DC converter 6 and an inverter 9. At this time, the data driver 1b inputs a data signal to each data line of the LCD panel 1, and the gate driver 1a applies a gate driving pulse to each gate line of the LCD panel 1. Then, the timing controller 3 receives display data R/G/B, vertical and horizontal synchronized signals VSY and HSY, a clock signal DCLK and a control signal DTEN from a driving system 7 of the LCD panel, and formats the display data, the clock signal and the control signal at a timing suitable for restoring a picture image by the gate driver 1a and the data driver 1b of the LCD panel 1. Also, the gamma reference voltage part 5 receives power from the power supply part 4 to provide a reference voltage required when digital data input from the data driver 1b is converted to analog data. The AC/DC converter 6 outputs a constant voltage VDD, a gate high voltage VGH, a gate low voltage VGL, a reference voltage Vref, and a common voltage Vcom for the LCD panel 1 by using a voltage output from the power supply part 4. Also, the inverter 9 drives the backlight 8.
An operation of the general LCD device in FIG. 1 will be described as follows. The timing controller 3 receives the display data R/G/B, the vertical and horizontal synchronous signals Vsync and Hsync, the clock signal DCLK and the control signal DTEN from the driving system PC 7 of the LCD panel, and provides the display data, the clock signal and the control signal formatted at the timing suitable for restoring the picture image by the data driver 1b and the gate driver 1a of the LCD panel 1. That is, the gate driver 1a applies the gate driving pulse to each gate line of the LCD panel 1, and the synchronous data driver 1b inputs the data signal to each data line of the LCD panel 1, thereby displaying the input picture image. At this time, the backlight 8 provides constant brightness without relation to the luminance of the input image signal.
As technology develops, the LCD device is used for a display device of a television requiring a rapid response time. Furthermore, a wide mode LCD device having an aspect ratio of 16 to 9 is being actively studied. The wide mode LCD device has a horizontal axis longer than that of the normal mode LCD device having the aspect ratio of 4 to 3. That is, in order to drive the normal mode image signal in the wide mode LCD device, black display is generated at the left and right sides of the display device.
A general driving method for displaying the normal mode image signal in the wide mode LCD device will be described as follows.
FIG. 2 is a timing view illustrating an analog normal mode driving method used in a general wide mode LCD device according to the related art. For example, in case a wide mode LCD device having a resolution of 1440×234 (the number of gate lines=234, the number of data lines=1440) receives a broadcasting signal used in Korea, an image signal of National Television Standard Committee (NTSC) method, a display method will be described as follows. In the LCD device having the resolution of 1440×234, one pixel is operated by three data lines R, G and B, and the number of pixels substantially operated is 480×234. Accordingly, in order to drive the normal mode image signal in the wide mode LCD device of which one line has 480 pixels, black display is generated at the left and right sides of the display device, in which about 60 pixels are displayed as black.
As shown in FIG. 2, one horizontal block (63.5 μs) of an analog image signal of the NTSC method includes a horizontal front porch 1.5 μs, a horizontal synchronous width (4.7 μs), a horizontal back porch (4.7 μs), and an active data period (52.6 μs). The horizontal front porch 1.5 μs indicates a time period from the active data of a preceding horizontal block (last pixel data of one line) to the falling edge of the horizontal synchronous signal HSY. The horizontal back porch 4.7 μs indicates a time period from the rising edge of the horizontal start pulse HSP to the start of the active data.
When displaying the broadcasting signal in the wide mode LCD device as the wide mode, the timing controller 3 divides the main clock signal 104.8 ns into two main clock signals as 52.4 ns, thereby outputting a source sampling clock SSC signal (latching the image data according to its rising or falling edge). Also, a source start pulse SSP (informing a data start point (a first pixel) in one horizontal block) is output to be positioned at a start point of a valid data block, so that 480 pixels of data are latched at the same clock signal, thereby outputting valid analog data for 50.3 μs. That is, the horizontal start pulse HSP is output with its falling edge synchronized with the rising edge of the horizontal synchronized signal HSY. The SSP is output after 6.28 μs (52.4 ns*60) from the rising edge of the horizontal start pulse HSP, thereby driving 480 pixels.
When displaying the broadcasting signal in the wide mode LCD device as the normal mode, the SSP is output such that the falling edge of the SSP is synchronized with the end of the horizontal back porch. In this regard, the start and end points of the active data region in one horizontal block are displayed abnormally, whereas the rest portions are displayed normally. By using a main clock signal (52.4 ns) input at the SSP start point, the image is abnormally displayed during a time period 3.14 μs (52.4 ns*60) corresponding to 60 pixels. Then subsequent 360 pixels are latched to the clock signal of 139.73 ns, and the valid analog data is output during 50.3 μs. Then, the data of subsequent 60 pixels is abnormally displayed for a time period of 3.14 μs by using the main clock signal (52.4 ns) again.
However, the driving method for displaying the normal mode image signal in the wide mode LCD device according to the related art has the following disadvantages.
In case of displaying the normal mode image signal in the wide mode LCD device, as mentioned above, specific pixels (60 pixels) are abnormally displayed at the start and end points of the active data region. But, the black display is not generated in the block having a transition area TA in the video signal since the beginning 60 pixel data is latched not to the back porch portion of the signal receiving the black data, but is latched to the transition area TA of the video signal. As a result, an undesired picture data is applied. This displays undesired lines and not the black display on the displayed screen. As a result, the picture quality is deteriorated.